1. Field of the Invention
The present invention relates to a thin film transistor (TFT) array substrate, and more particularly, to a TFT array substrate capable of preventing pad corrosion as well as protecting a TFT without any passivation layer, and the fabrication method thereof.
2. Discussion of the Related Art
A liquid crystal display device (LCD) displays an image by controlling the light transmittance of liquid crystal (LC) using an electric field.
The LCD drives liquid crystal using an electric field formed between a pixel electrode and a common electrode respectively disposed on an upper substrate and a lower substrate facing each other.
The LCD has a TFT array substrate (lower array substrate) and a color filter array substrate (upper array substrate) facing each other, a spacer disposed between the two array substrates to maintain a cell gap, and liquid crystal filling the cell gap.
The TFT array substrate includes signal lines, TFTs, and an alignment layer coated thereon to align the LC.
The color filter array substrate includes a color filter for reproducing colors, a black matrix (BM) for preventing light leakage, and an alignment layer coated thereon for aligning the LC.
In the LCD, as the TFT array substrate requires a semiconductor process and a plurality of mask processes, the manufacturing process thereof is complicated and thus the manufacturing cost increases.
To solve this problem, it is desired to develop a TFT array substrate that reduces the number of mask processes.
The reason for this is that one mask process may include many processes such as a thin film deposition process, a cleaning process, a photolithography process, an etching process, a photoresist stripping process, and an inspection process.
Recently, a 4-mask process requiring one less mask process than a standard 5-mask process that was typical for a TFT array substrate has been developed.
FIG. 1 is a plan view of a related art TFT array substrate fabricated using a 4-mask process, and FIG. 2 is a sectional view taken along line I-I′ in FIG. 1.
Referring to FIGS. 1 and 2, the related art TFT array substrate of a liquid crystal panel includes a lower substrate 1, a gate line 2, and a data line 4 formed on the lower substrate crossing each other with a gate insulating layer 12 in between, a TFT 30 formed at each crossing, a pixel electrode 22 formed in a pixel region defined by the crossing gate and data lines, a storage capacitor 40 formed at an overlapping area of the gate line 2 and a storage electrode 28, a gate pad 50 connected to the gate line 2, and a data pad 60 connected to the data line 4.
The gate line 2 supplying a gate signal and the data line 4 supplying a data signal are formed in a crossing structure to define a pixel region 5.
The TFT 30 allows a pixel signal on the data line 4 to be charged and maintained at the pixel electrode 22 in response to the gate signal of the gate line. The TFT 30 includes a gate electrode 6 connected to the gate line 2, a source electrode 8 connected to the data line 4, and a drain electrode 10 connected to the pixel electrode 22.
The TFT 30 further includes an active layer 14 that overlaps the gate electrode 6 with the gate insulating layer 12 between, to form a channel in between the source electrode 8 and the drain electrode 10.
The active layer 14 overlaps the data line 4, a data pad lower electrode 62, and the storage electrode 28.
An ohmic contact layer is further formed on the active layer 14 that provides 16 an ohmic contact with the data line 4, the source electrode 8, the drain electrode 10, the data pad lower electrode 62, and the storage electrode 28.
The pixel electrode 22 is formed in the pixel region 5 and connected to the drain electrode 10 of the TFT 30 through a first contact hole 20 that penetrates a passivation layer 18.
An electric field is formed between the pixel electrode 22 to which a pixel signal is applied through the TFT 30 and a common electrode (not shown) to which a reference voltage is applied. Liquid crystal molecules between the lower array substrate and an upper array substrate are rotated due to dielectric anisotropy by the electric field.
The light transmittance of the pixel region 5 is changed according to the rotational degree of the liquid crystal molecules, so that a gray scale is realized.
The storage capacitor 40 includes the gate line 2 and a storage electrode 28 that overlaps the gate line 2 with the gate insulating layer 12, the active layer 14, and the ohmic contact layer 16 in between.
The storage electrode 28 is connected to the pixel electrode 22 through a second contact hole 42 formed in the passivation layer 18.
The storage capacitor 40 allows a pixel signal charged on the pixel electrode 22 to be stably maintained until a next pixel signal is charged.
The gate pad 50 is connected to a gate driver (not shown) to apply a gate signal to the gate line 2. The gate pad 50 includes a gate pad lower electrode 52 extending from the gate line 2 and a gate pad upper electrode 54 connected to the gate pad lower electrode 52 through a third contact hole 56 that penetrates the gate insulating layer 12 and the passivation layer 18.
The data pad 60 is connected to a data driver (not shown) to apply a data signal to the data line 4. The data pad 60 includes a data pad lower electrode 62 extending from the data line 4 and a data pad upper electrode 64 connected to the data pad lower electrode 62 through a fourth contact hole 66 that penetrates the passivation layer 18.
A method of fabricating a TFT array substrate of a liquid crystal panel using a 4-mask process will be described in detail with reference to FIGS. 3A to 3D.
Referring to FIG. 3A, a first conductive pattern group including a gate line 2, a gate electrode 6, and a gate pad lower electrode 52 is formed on a lower substrate 1 using a first mask process.
A gate metal layer is formed on the lower substrate 1 using a deposition method (e.g., a sputtering method).
Then, the gate metal layer is patterned by a photolithography process and an etching process that use a first mask, so that the first conductive pattern group including the gate line 2, the gate electrode 6, and the gate pad lower electrode 52 is formed.
Referring to FIG. 3B, a gate insulating layer 12 is coated on the lower substrate 1 on which the gate pattern is formed.
Thereafter, a semiconductor pattern including an active layer 14 and an ohmic contact layer 16; and a second conductive pattern group including, a data line 4, a source electrode 8, a drain electrode 10, and a data pad lower electrode 62, and a storage electrode 28 are formed on the gate insulating layer 12 using a second mask process.
Referring to FIG. 3C, a passivation layer 18 including first to fourth contact holes 20, 42, 56 and 66 is formed by a second mask process on the gate insulating layer 12 on which the second conductive pattern group is formed. The passivation layer 18 is formed by a deposition method (e.g., a plasma enhanced chemical vapor deposition (PECVD)) on the entire surface of the gate insulating layer 12 on which the data pattern is formed.
Thereafter, the passivation layer 18 is patterned through a photolithography process and an etching process that use a third mask, so that the first to fourth contact holes 20, 42, 56, and 66 are formed.
The first contact hole 20 penetrates the passivation layer 18 to expose the drain electrode 10, and the second contact hole 42 penetrates the passivation layer 18 to expose the storage electrode 28.
The third contact hole 56 penetrates the passivation layer 18 and the gate insulating layer 12 to expose the gate pad lower electrode 52, and the fourth contact hole 66 penetrates the passivation layer 18 to expose the data pad lower electrode 62.
Referring to FIG. 3D, a third conductive pattern group including a pixel electrode 22, a gate pad upper electrode 54, and a data pad upper electrode 64 is formed on the passivation layer 18 using a fourth mask process.
The related art TFT array substrate has the passivation layer 18 to protect the TFT 30.
The passivation layer 18 is formed by depositing inorganic insulation material using a PECVD apparatus, or coating an organic insulation material using a spin coating apparatus or a spinless coating apparatus.
Because the PECVD apparatus, the spin coating apparatus, or the spinless coating apparatus are required to form the passivation layer 18 as descried above, the manufacturing cost increases.
Also, because the data line 4 is formed using a single layer, it is frequently opened. In this case, a separate process is required to repair the opened data line 4.
Also, when the passivation layer 18 is formed of an organic insulation material, the pixel electrode 22 may be disconnected due to the relatively thick passivation layer 18.
Particularly, the pixel electrode 22 is disconnected at the side of the passivation layer 18 exposed by the contact hole 20 for allowing the drain electrode 10 to contact with the pixel electrode 22.
Accordingly, because a pixel signal is not applied to the pixel electrode 22 through the drain electrode 10, a point defect is generated.
Also, the storage capacitor 40 includes the gate line 2 and the storage electrode 28 that overlap each other with the gate insulating layer 12, the active layer 14, and the ohmic contact layer 16 in between.
In this case, the capacitance of the storage capacitor 40 is degraded by the relatively thick gate insulating layer 12 that insulates the gate line 2 from the storage electrode 28, the active layer 14, and the ohmic contact layer 16.
Also, image quality degradation (e.g., spots) results due to the relatively low capacitance of the storage capacitor 40.
Also, because the data pad is opened when the passivation layer is formed, a defect (e.g., galvanic corrosion of a data pad) may be generated during a subsequent process.